1. Technical Field
Embodiments relate to a three dimensional (3D) semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device having a wrap-around contact structure and a method of manufacturing the same.
2. Related Art
Memory devices are generally provided as internal semiconductor integrated circuit devices of computers or other electronic apparatuses. Typical examples of memory devices include random access memories (RAMs), read only memories (ROMs), dynamic RAMs (DRAMs), synchronous DRAM (SDRAM), flash memories, and variable resistive memory devices. Variable resistive memory devices include programmable conductive memory devices, resistive RAMs (ReRAMs), and phase-change RAMs (PCRAMs).
Nonvolatile memory devices may be used in broad electronic applications to provide high integration density, high reliability, and low power consumption.
Variable resistive memory devices may include a plurality of memory cells arranged in matrix form. The memory cells may include an access device such as a diode, a field effect transistor (FET), or a bipolar junction transistor (BJT). The access device may be coupled to a word line extending along a row of an array. Memory elements in the memory cells may be coupled to a bit line extending along a column of 1o the array. In this manner, the access device of the memory cell may select a word line coupled to a gate and the memory cell may be accessed through a row decoder which activates the rows of the memory cell.
Currently, a transistor having a 3D vertical channel structure is used as the access device of the memory cells to increase integration density. As is well-known, a transistor having the 3D vertical channel structure may include a pillar-shaped active region, a gate formed on an outer circumference of the active region, a drain formed in an upper portion of the active region, and a source formed in a lower portion of the active region or formed in a semiconductor substrate which is in contact with the lower portion of the active region. A heating electrode, a variable resistance layer, and a bit line are sequentially formed to be electrically coupled to the drain of the transistor, and thus the resistive memory cell is completed.
To obtain ohmic contact between the drain and the heating electrode, a silicide layer is formed between the drain and the heating electrode. Currently, endeavors for improving the operation current in the variable resistive memory device continue, and thus, technology for improving contact properties between the drain and the silicide layer or between a lower electrode and the silicide layer has been suggested.